asynchronous sequential circuit
英 [eɪˈsɪŋkrənəs sɪˈkwenʃl ˈsɜːkɪt]
美 [eɪˈsɪŋkrənəs sɪˈkwenʃl ˈsɜːrkɪt]
网络 异步时序电路
双语例句
- Interlocked flip-flop and its application to multi-input asynchronous sequential circuit design
互锁触发器及其在设计多输入异步时序电路中的应用 - A Standard Method to Find internal Clock Pulse Overlay Area by Karnaugh Map ── Analysis of Asynchronous Sequential Logic Circuit in the Case or Comples Clock Pulse
利用卡诺图寻找内时钟复盖区的规范方法&复杂时钟下异步时序罗辑电路分析 - In this article, the characteristic equation in asynchronous sequential circuit is further explained.
进一步说明、解释异步时序线路的特征表达式。 - This paper presents a new method to design asynchronous sequential circuit: clock signals and secondary state Karnaugy Map uniting method.
提出了一种异步时序电路设计的新方法：时钟信号与次态卡诺图联立法。 - Analysis on the Pulse Asynchronous Sequential logic circuit
脉冲型异步时序网络的分析 - Design of Asynchronous Sequential Logic Circuit Based on Design of Clock Signal
基于时钟设计的异步时序逻辑电路设计法 - After introducing the model of level asynchronous sequential circuit and the special hazard about race and hazard, it brings forward analysis way and solution to essential hazard about level asynchronous sequential circuit.
在介绍了电平异步时序逻辑电路的模型，电平异步时序电路的竞争冒险的特有的本质险象后，提出了电平异步时序电路的本质险象的分析判断方法和解决方案。 - The Discussion on the characteristic Equation in Asynchronous Sequential Circuit
论异步时序线路的特征表达式 - The Essential Hazard of the Level Asynchronous Sequential Circuit
电平异步时序电路的本质险象